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Multi-core processor
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121	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
122	Computer Systems CS3650 http://www.ccs.neu.edu/course/cs3650/ Spring, 2016 Professor G. Cooperman Add to Reading List Source URL: www.ccs.neu.edu Language: English - Date: 2016-01-02 16:08:06 System calls Application programming interfaces Concurrent computing Parallel computing Computer architecture Xv6 Thread CPU cache Fork POSIX Unix Multi-core processor
123	X-Gene 3 Challenges Xeon E5 By Linley Gwennap Principal Analyst April 2016 Add to Reading List Source URL: www.linleygroup.com Language: English - Date: 2016-04-19 20:31:26 Computer architecture Parallel computing Xeon Intel Core CPU sockets Skylake Broadwell Multi-core processor Performance per watt Applied Micro Circuits Corporation LGA Sandy Bridge-E
124	An Operational Semantics of Cache Coherent Multicore Architectures∗ Shiji Bijo, Einar Broch Johnsen, Ka I Pun, and S. Lizeth Tapia Tarifa University of Oslo, Norway {shijib, einarj, violet, sltarifa}@ifi.uio.no Add to Reading List Source URL: einarj.at.ifi.uio.no Language: English - Date: 2016-01-07 10:39:37 Cache coherency Parallel computing Computer architecture Computer memory computing CPU cache MSI protocol Coherent cache Cache MESI protocol Multi-core processor Draft:Cache memory
125	DEGAS: Dynamic Global Address Space programming environments Katherine Yelick, Principal Investigator1 Lawrence Berkeley National Laboratory, Berkeley, California Vivek Sarkar, Co-Principal Investigator2 Rice University, Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2016-04-02 22:06:19 Parallel computing Partitioned global address space Coarray Fortran Unified Parallel C X10 Parallel programming model Multi-core processor PGAS Matrix multiplication algorithm Fortran Distributed computing OpenMP
126	H-Store: A Specialized Architecture for High-throughput OLTP Applications Evan Jones (MIT) Andrew Pavlo (Brown) 13th Intl. Workshop on High Performance Transaction Systems Add to Reading List Source URL: hpts.ws Language: English - Date: 2012-04-19 12:03:41 Data management Databases Online transaction processing Transaction processing Microprocessors Nehalem Xeon Multi-core processor
127	A preliminary evaluation of the hardware acceleration of the Cray Gemini Interconnect for PGAS languages and comparison with MPI Hongzhang Shan, Nicholas J. Wright, John Shalf and Katherine Yelick CRD and NERSC Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-12-13 17:18:30 Parallel computing Message Passing Interface Partitioned global address space MPICH Coarray Fortran Cray Multi-core processor Blue Gene MVAPICH MPI K computer Parallel Virtual Machine
128	Adaptive Task Size Control on High Level Programming for GPU/CPU Work Sharing Tetsuya Odajima, Taisuke Boku, Mitsuhisa Sato, Toshihiro Hanawa, Yuetsu Kodama, Raymond Namyst, Samuel Thibault, Olivier Aumage To cite this Add to Reading List Source URL: hal.inria.fr Language: English - Date: 2016-07-28 14:43:35 Parallel computing GPGPU Graphics hardware Video cards Application programming interfaces General-purpose computing on graphics processing units Graphics processing unit Multi-core processor OpenCL Fermi GPU cluster Compute kernel
129	Noname manuscript No. (will be inserted by the editor) Multiprocessor Speed Scaling for Jobs with Arbitrary Sizes and Deadlines Paul C. Bell, Prudence W.H. Wong Add to Reading List Source URL: cgi.csc.liv.ac.uk Language: English - Date: 2013-04-09 08:32:08 Scheduling Operations research Combinatorial optimization Mathematical optimization Multiprocessor scheduling NC Multi-core processor Randomized algorithm Algorithm
130	Automatic Mapping of Parallel Applications on Multicore Architectures using the Servet Benchmark Suite Jorge Gonz´ alez-Dom´ınguez∗, Guillermo L. Taboada, Basilio B. Fraguela, Mar´ıa J. Mart´ın, Juan Touri˜ no Add to Reading List Source URL: gac.udc.es Language: English - Date: 2012-03-15 09:04:50 Parallel computing Multi-core processor Message Passing Interface OpenMP CPU cache Thread Supercomputer Computer cluster Partitioned global address space Symmetric multiprocessing Multiprocessing Benchmark

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